Architecture of microprocessor 8086 part2

Bus Interface Unit (BIU):-
  This unit contains following parts of 8086:-

• 6 byte instruction queue
• segment registers (CS,DS,ES,SS)
• instruction  pointer

 This unit performs following steps:-

•  Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture
• This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

•  These prefetching instructions are held in its FIFO queue.With its 16 bit data bus, the BIU fetches two instructionbytes in a single memory cycle.

•  After a byte is loaded at the input end of the queue, itautomatically shifts up through the FIFO to the emptylocation nearest the output.

• The EU accesses the queue from the output end. It readsone instruction byte after the other from the output of thequeue. If the queue is full and the EU is not requestingaccess to operand in memory.
•  These intervals of no bus activity, which may occur between bus cycles are known as Idle state.
•  If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle

• The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.

•  For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

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