Architecture of 8255 programmable peripheral device.

The Intel 8255A is a general purpose programmable I/O device which is

designed for use with all Intel and most other microprocessors.It provides 24 I/O pins which may be individually programmed in 2 groups of 1 and used in 3 major modes of operation.The 8255 is a 40 pin integrated circuit (IC), designed The 8255 is a 40 pin It designed by Intel for the 8080 microprocessor

Two control groups, labeled group A control and group B control define how the three I/O ports operate. There are several different operating modes for the 8255 and these modes must be defined by the CPU writing programming or control words to the device 8255.
The line group of port C consists of two 4 bit ports. One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control.
The final logic blocks are read/write control logic and data bus buffer. These blocks provide the electrical interface between the Z80 and the 8255.
The data bus buffer buffers the data I/O lines to/from the Z80 data bus. The read/write control logic routes the data to and from the correct internal registers with the right timing. The internal path being enabled depends on the type of operation performed by the Z80. The type of operation can be I/O read or I/O write.

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