Architecture of microprocessor 8086 part2

Bus Interface Unit (BIU):-
  This unit contains following parts of 8086:-

• 6 byte instruction queue
• segment registers (CS,DS,ES,SS)
• instruction  pointer

 This unit performs following steps:-

•  Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture
• This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

•  These prefetching instructions are held in its FIFO queue.With its 16 bit data bus, the BIU fetches two instructionbytes in a single memory cycle.

•  After a byte is loaded at the input end of the queue, itautomatically shifts up through the FIFO to the emptylocation nearest the output.

• The EU accesses the queue from the output end. It readsone instruction byte after the other from the output of thequeue. If the queue is full and the EU is not requestingaccess to operand in memory.
•  These intervals of no bus activity, which may occur between bus cycles are known as Idle state.
•  If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle

• The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.

•  For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

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Architecture of 8086 microprocessor part1

8086 microprocessor:-

 The microprocessor 8086 belongs from the group of 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978. it have data bus of 16- bit and address bus of 20-bit. it have memory of 1MB power supply of +5v. CPU clock rate is 5MHz to 10MHz. it have package of 40 pin IC. it have eight general purpose register including stack pointer base pointer and source index and destination index. four segment register and a program counter. it have 9 flag register.

• microprocessor- 16bit
• data bus           - 16bit
• address bus      - 20bit
• power supply   - +5v
• CPU clock rate- 5MHz to 10MHz
• package           - 40 pin IC
• memory           - 1MB

Block diagram of 8086:- 

 

It contains two parts EU and BIU.

Execution unit(EU):- this unit performs following steps.

• Decodes instructions fetched by BIU
• Generate control signals
• Executes instruction    

This unit contains 8 general purpose register

1. Accumulator register AX- AH and AL
2. Base register  BX- BH and BL
3. Count register CX- CH and CL
4. Data register   DX- DH and DL
5. SP- stack pointer
6. BP- base pointer
7. SI-  source index
8. DI- destination index   

Register AX,BX,CX and DX is of 16-bit each but it is devided into two registers high and low of 8-bit for each register. and we can use as  8-bit or 16-bit. two pointers are stack pointer and base pointer and two index registers are source index and destination index.

Arithmetic logic unit (ALU):- this unit performs arithmetic and logic operation.

Execution and control system:- this unit performs the process of execution and controls all the process of execution unit.

Flag register:- a flag is a flip flop which indicates some condition produced by the execution of an instruction. 8086 have nine 16-bit flag registers.

1. carry flag
2. sign flag
3. parity flag
4. auxiliary flag
5. zero flag
6. overflow flag
7. interrupt flag
8. direction flag
9. trap flag

it have five same flag register like 8085 and four different flag registers are overflow flag, interrupt flag, direction flag and trap flag.


Functions of execution unit:-

• The Execution unit is responsible for decoding and executing all instructions.

• The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write by cycles to memory or I/O and perform the operation specified by the instruction on the operands.

•  During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.

• If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.

•  When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.

• Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

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Posted in 8086 microprocessor